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Features
* 80C52 Compatible
- 8051 Pin and Instruction Compatible - Four 8-bit I/O Ports (or 6 in 64/68 Pins Packages) - Three 16-bit Timer/Counters - 256 bytes Scratch Pad RAM - 7 Interrupt Sources With 4 Priority Levels ISP (In-System Programming) Using Standard VCC Power Supply Boot Flash Contains Low Level Flash Programming Routines and a Default Serial Loader High-Speed Architecture - 40 MHz in Standard Mode - 20 MHz in X2 Mode (6 Clocks/Machine Cycle) 64K bytes On-chip Flash Program/Data Memory - Byte and Page (128 bytes) Erase and Write - 100K Write Cycles On-chip 1024 Bytes Expanded RAM (XRAM) - Software Selectable Size (0, 256, 512, 768, 1024 bytes) - 768 Bytes Selected at Reset for T87C51RD2 Compatibility Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals Improved X2 Mode with Independant Selection for CPU and Each Peripheral 2K bytes EEPROM Block for Data Storage - 100K Write Cycle Programmable Counter Array with - High Speed Output - Compare/Capture - Pulse Width Modulator Watchdog Timer Capabilities Asynchronous Port Reset Full-duplex Enhanced UART Low EMI (Inhibit ALE) - Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes: - Idle Mode - Power-down Mode Power Supply: - M version: Commercial and Industrial 4.5V to 5.5V: 40 MHz (X1 Mode), 20 MHz (X2 Mode) 3V to 5.5V: 33 MHz (X1 Mode), 16 MHz (X2 Mode) - L version: Commercial and industrial 2.7V to 3.6V: 25 MHz (X1 Mode), 12 MHz (X2 Mode) Temperature Ranges: Commercial (0 to +70C) and Industrial (-40 to +85C) Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64
* * * * * * * * *
0 to 40 MHz Flash Programmable 8-bit Microcontroller
T89C51RD2
* *
* *
Rev. 4243G-8051-05/03
1
Description
T89C51RD2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program and for data. The 64 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C51RD2 retains all features of the ATMEL 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the T89C51RD2 has a Programmable Counter Array, an XRAM of 1024 bytes, an EEPROM of 2048 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). Pinout is either the standard 40/44 pins of the C52 or an extended version with 6 ports in a 64/68 pins package. The fully static design of the T89C51RD2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51RD2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51RD2 makes it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. Table 1. Memory Size
PDIL40 PLCC44 VQFP44 1.4 T89C51RD2 Flash (bytes) 64K EEPROM (bytes) 2K XRAM (bytes) 1024 TOTAL RAM (bytes) 1280 I/O 32
PLCC68 VQFP64 1.4 T89C51RD2 Flash (bytes) 64K
EEPROM (bytes) 2K
XRAM (bytes) 1024
TOTAL RAM (bytes) 1280
I/O 48
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Block Diagram
T2EX VCC PCA RxD TxD Vss ECI T2 (1)
(3) (3) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA RD WR (3) (3) Timer 0 Timer 1 INT Ctrl Parallel I/O Ports & Ext. Bus EUART RAM 256x8
(1)
(1) (1)
Flash 64Kx8
XRAM
1Kx8
EEPROM
2Kx8
PCA
Timer2
C51 CORE
IB-bus
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 (2) (2)
Watch Dog
(3) (3) RESET T0 T1
(3) (3) P1 P2 P3 P4 INT0 INT1 P0 P5
Notes:
1. Alternate function of Port 1. 2. Only available on high pin count packages. 3. Alternate function of Port 3.
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Pin Configuration
P1.0/T2 P1.1/T2EX P1.2/ECI P1.3CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7CEX4 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0/AD0 P1.4/CEX1 P1.3/CEX0 P1.1/T2EX P0.2/AD2 P0.3/AD3 39 38 37 36 35 34 33 32 31 30 29 P0.0/AD0 P0.1/AD1 P1.2/ECI P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE/PROG PSEN P2.7/AD15 P2.6/AD14 P2.5/AD13 P2.4/AD12 P2.3/AD11 P2.2/AD10 P2.1/AD9 P2.0/AD8 P1.5/CEX2 P1.6/CEX3 P1.7/CEx4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
P1.0/T2
PDIL
PLCC
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR P2.2/A10 P2.3/A11 P2.4/A12 P3.7/RD NIC* P2.0/A8 P2.1/A9 XTAL2 XTAL1 VSS
P1.4/CEX1
P1.3/CEX0
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
VQFP44 1.4
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11 P2.4/A12 XTAL1 P2.1/A9 P2.2/A10 P3.6/WR P3.7/RD NIC* P2.0/A8 XTAL2 VSS
Note:
NIC = No Internal Connection
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P0.3/AD3
P1.2/ECI
P1.0/T2
NIC*
VCC
VCC
NIC*
T89C51RD2
P0.5/AD5
P0.6/AD6
P0.4/AD4
P0.7/AD7
ALE/PROG
P2.7/A15
P2.6/A14
9 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS1 P1.0/T2 P4.0 P1.1/T2EX P1.2/ECI P1.3/CEX0 P4.1 P1.4/CEX1 P4.2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P5.0 P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3.6/WR P4.3
PLCC 68 PLCC68
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RST NIC NIC NIC NIC NIC P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 P3.0/RxD NIC NIC P3.1/TxD P3.4/T0 P3.2/INT0 P3.3/INT1 P3.5/T1
P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS1 P1.0/T2 P4.0 P1.1/T2EX P1.2/EC1 P1.3/CEX0 P4.1 P1.4/CEX1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0.4/AD4 P5.4 P5.3 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC ALE/PROG PSEN P2.7/A15 P2.6/A14 P5.2 P5.1 P2.5/A13 P5.0
VQFP64 1.4 VQFP64 1.4
P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3.6/WR P4.3
P4.2 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST NIC NIC NIC P3.0/RxD NIC NIC P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1
P2.5/A13 53 52 51 50 49 48 47 46 45
NIC
P5.4
P5.3
NIC
PSEN NIC
P5.2
P5.1
EA
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Table 2. Pin Description
Pin Number Mnemonic VSS Vss1 VCC P0.0-P0.7 40 39-32 DIL 20 LCC 22 1 44 43-36 VQFP 1.4 16 39 38 37-30 Type I I I I/O Name and Function Ground: 0V reference Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for TSC8x54/58 Port 1 include: 1 2 3 4 5 6 7 8 P2.0-P2.7 21-28 2 3 4 5 6 7 8 9 24-31 40 41 42 43 44 1 2 3 18-25 I/O I I I/O I/O I/O I/O I/O I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock for the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for RB devices P2.0 to P2.6 for RC devices P2.0 to P2.7 for RD devices. P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. RXD (P3.0): Serial input port TXD (P3.1): Serial output port
P1.0-P1.7
1-8
2-9
40-44 1-3
I/O
10 11
11 13
5 7
I O
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Table 2. Pin Description (Continued)
Pin Number Mnemonic DIL 12 13 14 15 16 17 Reset 9 LCC 14 15 16 17 18 19 10 VQFP 1.4 8 9 10 11 12 13 4 Type I I I I O O I/O Name and Function INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier
ALE/PROG
30
33
27
O (I)
PSEN
29
32
26
O
EA
31
35
29
I
XTAL1
19
21
15
I
XTAL2
18
20
14
O
7
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SFR Mapping
The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories: * * * * * * * * * C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3, P4, P5 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON Hardware Watchdog Timer register: WDTRST, WDTPRG Interrupt system registers: IE, IP, IPH Flash and EEPROM registers: FCON, EECON, EETIM Others: AUXR, AUXR1, CKCON
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Table 3 below shows all SFRs with their address and their reset value. Table 3. SFR Table
Bit Addressable 0/8 F8h B 0000 0000 P5 1111 1111 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 T2CON 0000 0000 P4 1111 1111 IP X000 000 P3 1111 1111 IE 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR XX0X 1000 CKCON X000 0000 PCON 00X1 0000 7/F SBUF XXXX XXXX SADDR 0000 0000 AUXR1 XXXX 00X0 WDTRST XXXX XXXX WDTPRG XXXX X000 SADEN 0000 0000 IPH X000 0000 CMOD 00XX X000 FCON XXXX 0000 T2MOD XXXX XX00 CCAPM0 X000 0000 EECON XXXX XX00 RCAP2L 0000 0000 CCAPM1 X000 0000 EETIM 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 P5 1111 1111 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 CL 0000 0000 CCAP0L XXXX XXXX CCAP1L XXXX XXXX CCAP2L XXXX XXXX CCAP3L XXXX XXXX CCAP4L XXXX XXXX 1/9 CH 0000 0000 2/A CCAP0H XXXX XXXX 3/B CCAP1H XXXX XXXX Non Bit addressable 4/C CCAP2H XXXX XXXX 5/D CCAP3H XXXX XXXX 6/E CCAP4H XXXX XXXX 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h
DFh
D0h
D7h
C8h
CFh
C0h
C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
reserved
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Enhanced Features
In comparison to the original 80C52, the T89C51RD2 implements some new features, which are: * * * * * * * * * * The X2 option The Dual Data Pointer The extended RAM The Programmable Counter Array (PCA) The Watchdog The 4 level interrupt priority system The power-off flag The ONCE mode The ALE disabling Some enhanced features are also located in the UART and the Timer 2
X2 Feature and Clock Generation
The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called "X2" provides the following advantages: * * * * Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is validated on XTAL1/2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2 shows the mode switching waveforms. Figure 1. Clock Generation Diagram
XTAL1 FXTAL 2 XTAL1:2 0 1 FOSC X2 CKCON reg State Machine: 6 clock cycles. CPU control.
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Figure 2. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock STD Mode X2 Mode STD Mode
The X2 bit in the CKCON register (Table 4) allows to switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (Table 4) allow to switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode. More information about the X2 mode can be found in the application note ANM072 "How to take advantage of the X2 features in TS80C51 microcontroller". Table 4. CKCON Register CKCON - Clock Control Register (8Fh)
7 Bit Number 7 6 WdX2 Bit Mnemonic Description Reserved Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PcaX2 4 SiX2 3 T2X2 2 T1X2 1 T0X2 0 X2
6
WdX2
5
PcaX2
4
SiX2
3
T2X2
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Bit Number
Bit Mnemonic Description Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle CPU clock
2
T1X2
1
T0X2
0
X2
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.
Reset Value = X000 0000b Not bit addressable
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Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3). Figure 3. Use of Dual Pointer
External Data Memory
7
0 DPS
DPTR1 DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
Table 5. AUXR1: Auxiliary Register 1
AUXR1 Address 0A2H Reset value Symbol DPS Function Not implemented, reserved for future use. (1) Data Pointer Selection. DPS 0 1 GF3 Operating Mode DPTR0 Selected DPTR1 Selected X X X X GF3 0 0 0 X DPS 0
This bit is a general purpose user flag(2).
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 2. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
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Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a 'source' pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE
; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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Expanded RAM (XRAM)
The T89C51RD2 provide additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. T89C51RD2 devices have expanded RAM in external data space; Maximum size and location are described in Table 6. Table 6. Description of Expanded RAM
Address Port T89C51RD2 1024 XRAM size Start 00h End 3FFh
The T89C51RD2 has internal data memory that is mapped into four separate segments. The four segments are: * * * * 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register. (See Table 7.)
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. Figure 4. Internal and External Data Memory Address
FF or 3FF FF Upper 128 bytes Internal Ram indirect accesses XRAM 80 80 FF FFFF
Special Function Register direct accesses
External Data Memory
Lower 128 bytes Internal Ram direct or indirect accesses 00 00
0100 or 0400 0000
When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. * Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR at location 0A0H (which is P2).
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*
Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 7. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done thanks to the use of DPTR. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).
*
*
*
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
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Table 7. Auxiliary Register (08EH)
AUXR Address 08EH Reset value Symbol AO Function Not implemented, reserved for future use. (1) Disable/Enable ALE AO 0 1 EXTRAM Operating Mode ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) ALE is active only during a MOVX or MOVC instruction X X M0 0 X XRS1 1 XRS0 0 EXTRA M 0 AO 0
Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAM 0 1 Operating Mode Internal XRAM access using MOVX @ Ri/ @ DPTR External data memory access
XRS0 XRS1
XRAM size: Accessible size of the XRAM XRS1:0 00 01 10 11 XRAM size 256 bytes 512 bytes 768 bytes (default) 1024 bytes
M0
Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0 M0 0 1 Pulse length in clock period 6 30
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
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Timer 2
The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 8) and T2MOD register (See Table 9). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware description. Refer to the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In T89C51RD2 Timer 2 includes the following enhancements: * * Auto-reload mode with up or down counter Programmable clock-output
Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 5. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)
XTAL1 FXTAL FOSC T2 C/T2 T2CONreg TR2 T2CONreg :12 0 1
(DOWN COUNTING RELOAD FFh FFh (8-bit) (8-bit)
T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up TOGGL T2CONreg EXF2
TL2 (8-bit)
TH2 (8-bit)
TF2 T2CONreg
TIMER 2 INTERRUPT
RCAP2L RCAP2H (8-bit) (8-bit) (UP COUNTING RELOAD VALUE)
Programmable Clock-Output
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers : F osc Clock - OutFrequency = ------------------------------------------------------------------------------------------4 x ( 65536 - RCAP2H RCAP2L ) For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: * * * * * Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
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Figure 6. Clock-Out Mode C/T2 = 0
XTAL1 :2
TR2 T2CON reg TL2 (8-bit) TH2 (8-bit) OVEFLOW
RCAP2L (8-bit) Toggle T2 Q D
RCAP2H (8-bit)
T2OE T2MOD reg T2EX EXEN2 T2CON reg EXF2 T2CON reg TIMER 2 INTERRUPT
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Table 8. T2CON Register T2CON - Timer 2 Control Register (C8h)
7 TF2 Bit Number 6 EXF2 Bit Mnemonic Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn't cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 9. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. 5 4 3 2 1 T2OE 0 DCEN
6
-
5
-
4
-
3
-
2
-
1
T2OE
0
DCEN
Reset Value = XXXX XX00b Not bit addressable
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T89C51RD2
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T89C51RD2
Programmable Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be programmed to count any one of the following signals: * * * * * * * * Oscillator frequency / 12 (/ 6 in X2 mode) Oscillator frequency / 4 (/ 2 in X2 mode) Timer 0 overflow External input on ECI (P1.2) rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator.
Each compare/capture modules can be programmed in any one of the following modes:
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 32). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If one or several bits in the port are not used for the PCA, they can still be used for standard I/O.
PCA component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 16-bit Module 4 External I/O Pin P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3 P1.7 / CEX4
The PCA timer is a common time base for all five modules (See Figure 7). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 10) and can be programmed to run at: * * * * 1/12 the oscillator frequency. (Or 1/6 in X2 Mode) 1/4 the oscillator frequency. (Or 1/2 in X2 Mode) The Timer 0 overflow The input on the ECI pin (P1.2)
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Figure 7. PCA Timer/Counter
To PCA modules Fosc /12 Fosc / 4 T0 OVF P1.2 CH CL 16 bit up/down counter overflow It
CIDL Idle
WDTE
CPS1
CPS0
ECF
CMOD 0xD9
CF
CR
CCF4 CCF3
CCF2
CCF1
CCF0
CCON 0xD8
Table 10. CMOD: PCA Counter Mode Register
CMOD Address 0D9H Reset value Symbol CIDL Function Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. Not implemented, reserved for future use. (1) PCA Count Pulse Select bit 1. PCA Count Pulse Select bit 0. CPS 1 0 0 1 1 ECF CPS 0 0 1 0 1 Selected PCA input. (2) Internal clock fosc/12 ( Or fosc/6 in X2 Mode). Internal clock fosc/4 ( Or fosc/2 in X2 Mode). Timer 0 Overflow External clock at ECI/P1.2 pin (max rate = fosc/ 8) CIDL 0 WDT E 0 X X X CPS1 0 CPS0 0 ECF 0
WDTE CPS1 CPS0
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. fosc = oscillator frequency
2.
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T89C51RD2
The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 10). * * * The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on module 4. The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 11). * * Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software.
*
Table 11. CCON: PCA Counter Control Register
CCON Address 0D8H Reset value Symbol Function PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use. (1) PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CF 0 CR 0 X CCF4 0 CCF3 0 CCF2 0 CCF1 0 CCF0 0
CF
CR CCF4
CCF3
CCF2
CCF1
CCF0
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
The watchdog timer function is implemented in module 4 (See Figure 10).
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The PCA interrupt system is shown in Figure 8. Figure 8. PCA Interrupt System
CF PCA Timer/Counter CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8
Module 0
Module 1
To Interrupt priority decoder
Module 2
Module 3
Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IE.6 EC IE.7 EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: * * * * * * 16-bit Capture, positive-edge triggered, 16-bit Capture, negative-edge triggered, 16-bit Capture, both positive and negative-edge triggered, 16-bit Software Timer, 16-bit High Speed Output, 8-bit Pulse Width Modulator.
In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 12). The registers contain the bits that control the mode that each module will operate in. * The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition.
* *
*
*
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* The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 13 shows the CCAPMn settings for the various PCA functions. . Table 12. CCAPMn: PCA Modules Compare/Capture Control Registers
CCAPMn Address n=0-4 CCAPM0=0DAH CCAPM1=0DBH CCAPM2=0DCH CCAPM3=0DDH CCAPM4=0DEH Reset value Symbol ECOMn CAPPn CAPNn MATn Function Not implemented, reserved for future use. (1) Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. X ECO Mn 0 CAPP n 0 CAPN n 0 MATn 0 TOGn 0 PWM m 0 ECCF n 0
TOGn
PWMn
ECCFn
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Table 13. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn 0 X 0 1 CAPNn 0 0 MATn 0 0 TOGn 0 0 PWMm 0 0 ECCFn 0 X Module Function No Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer / Compare mode. 16-bit High Speed Output 8-bit PWM
X
0
1
0
0
0
X
X
1
1
0
0
0
X
1 1 1
0 0 0
0 0 0
1 1 0
0 1 0
0 0 1
X X 0
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ECOMn CAPPn 1 0
CAPNn 0
MATn 1
TOGn X
PWMm 0
ECCFn X
Module Function Watchdog Timer (module 4 only)
There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 14 & Table 15) Table 14. CCAPnH: PCA Modules Capture/Compare Registers High
CCAPnH Address n=0-4 CCAP0H=0FAH CCAP1H=0FBH CCAP2H=0FCH CCAP3H=0FDH CCAP4H=0FEH 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 15. CCAPnL: PCA Modules Capture/Compare Registers Low
CCAPnL Address n=0-4 CCAP0L=0EAH CCAP1L=0EBH CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 16. CH: PCA Counter High
CH Address 0F9H 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 17. CL: PCA Counter Low
CL Address 0E9H 7 Reset value 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
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PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCONSFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 9).
Figure 9. PCA Capture Mode
CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA IT
PCA Counter/Timer Cex.n Capture CH CL
CCAPnH
CCAPnL
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE
16-bit Software Timer/ Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 10).
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Figure 10. PCA Compare Mode and PCA Watchdog Timer
CCON CF Write to CCAPnL Write to CCAPnH 1 0 Enable 16 bit comparator RESET * Reset PCA IT CCAPnH CCAPnL Match CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
CH
CL
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4 0xDA to 0xDE
CIDL
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
* Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 11). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
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T89C51RD2
Figure 11. PCA High Speed Output Mode
CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
Write to CCAPnL Reset
PCA IT Write to CCAPnH 0 CCAPnH Enable 16 bit comparator CCAPnL Match
1
CH
CL
CEXn
PCA counter/timer CCAPMn, n = 0 to 4 0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
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Figure 12. PCA PWM Mode
CCAPnH Overflow
CCAPnL "0" Enable 8 bit comparator
< S
"1"
CEXn
CL PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n= 0 to 4 0xDA to 0xDE
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 10 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: * * * 1. periodically change the compare value so it will never match the PCA timer, 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won't generate a reset out on the reset pin.
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T89C51RD2
Serial I/O Port
The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: * * Framing Error Detection Framing error detection Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 13). Figure 13. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) SMOD1SMOD0 POF GF1 GF0 PD IDL PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 20.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.). Figure 14. UART Timings in Mode 1
RXD Start bit RI SMOD0=X FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
Data byte
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Figure 15. UART Timings in Modes 2 and 3
RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit Data byte
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb
Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b
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The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.:
SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN1111 111Xb
The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b,
Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b
For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don't-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. Table 18. SADEN - Slave Address Mask Register (B9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable
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Table 19. SADDR - Slave Address Register (A9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable Table 20. SCON Register SCON - Serial Control Register (98h)
7 FE/SM0 Bit Number 6 SM1 Bit Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit Serial port Mode bit 1 SM0 SM1 Mode Description 6 SM1 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART Baud Rate FXTAL/12 (/6 in X2 mode) Variable FXTAL/64 or FXTAL/32 (/32 or 16 in X2 mode) Variable 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
7
FE
SM0
5
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
4
REN
3
TB8
Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and Figure 15. in the other modes.
2
RB8
1
TI
0
RI
Reset Value = 0000 0000b Bit addressable
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Table 21. PCON Register PCON - Power Control Register (87h)
7 SMOD1 6 SMOD0 Bit Bit Number 7 Mnemoni c Description SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn't affect the value of this bit.
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Interrupt System
The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16.
Figure 16. Interrupt Control System
IPH, IP 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 3 PCA IT 0 RI TI 3 0 3 0 Interrupt polling sequence, decreasing from high to low priority High priority interrupt
TF2 EXF2
Individual Enable
Global Disable
Low priority interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 23.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 24.) and in the Interrupt Priority High register (See Table 22). shows the bit values and priority levels associated with each combination. Table 22. Priority Level Bit Values
IPH.x 0 0 1 1 IP.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest)
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A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 23. IE Register IE - Interrupt Enable Register (A8h)
7 EA Bit Number 6 EC Bit Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. PCA interrupt enable bit Clear to disable . Set to enable. Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
7
EA
6
EC
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b Bit addressable
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Table 24. IP Register IP - Interrupt Priority Register (B8h)
7 Bit Number 7 6 PPC Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. Serial port Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level. 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
6
PPC
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Reset Value = X000 0000b Bit addressable
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Table 25. IPH Register IPH - Interrupt Priority High Register (B7h)
7 Bit Number 7 6 PPCH Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit high. PPC Priority Level PPCH 0 0 Lowest 0 1 1 0 1 1 Highest 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
6
PPCH
5
PT2H
Timer 2 overflow interrupt Priority High bit PT2 Priority Level PT2H 0 0 Lowest 0 1 1 0 1 1 Highest Serial port Priority High bit PS Priority Level PSH 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit PX1 Priority Level PX1H 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PT0 Priority Level PT0H 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
4
PSH
3
PT1H
2
PX1H
1
PT0H
0
PX0H
Reset Value = X000 0000b Not bit addressable
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Power Management
Two power reduction modes are implemented in the T89C51RD2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section "X2 Feature". In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin. A bad level leads to a wrong initialization of the internal registers like SFRs, Program Counter... and to unpredictable behavior of the microcontroller. A proper device reset initializes the T89C51RD2 and vectors the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VDD as shown in Figure 17. A warm reset can be applied either directly on the RST pin or indirectly by an internal reset source such as the watchdog timer. Resistor value and input characteristics are discussed in the Section "DC Characteristics" of the T89C51RD2 datasheet. Figure 17. Reset Circuitry and Power-On Reset
VDD
Reset
From Internal Reset Source To CPU Core and Peripherals
VDD
P
RST
RRST
+
RST
VSS
RST input circuitry
Power-on Reset
Cold Reset
2 conditions are required before enabling a CPU start-up: * * VDD must reach the specified VDD range The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the RST pin must be maintained till both of the above conditions are met. A reset is active when the level V IH1 is reached and when the pulse width covers the period of time where VDD and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width: * * VDD rise time, Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. Table 26 gives some capacitor values examples for a minimum RRST of 50 K and different oscillator startup and VDD rise times.
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Table 26. Minimum Reset Capacitor Value for a 50 k Pull-down Resistor(1)
Oscillator Start-Up Time 5 ms 20 ms Note: VDD Rise Time 1 ms 820 nF 2.7 F 10 ms 1.2 F 3.9 F 100 ms 12 F 12 F
These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1). As detailed in Section "Watchdog Timer", the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown Figure 18. Figure 18. Reset Circuitry for WDT Reset-out Usage
VDD
Watchdog Reset
+
VDD
From WDT Reset Source To CPU Core and Peripherals
RST
VDD
1K
P
RST
RRST
VSS
VSS
To Other On-board Circuitry
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Reset Recommendation to Prevent Flash Corruption
Since the product includes a software area (booloader) where the C51 core can operate Flash write operations, if the value of the Program Counter is accidently in the range of the boot memory addresses then a Flash access (write or erase) may corrupt the Flash on-chip memory. It is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage (power supply failure, power supply switched off).
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high level. There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle. For example, an instruction that activates idle can also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a Power-down mode can be invoked by software (see Table 14, PCON register). In Power-down mode, the oscillator is stopped and the instruction that invoked Powerdown mode is the last instruction executed. The internal RAM and SFRs retain their value until the Power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from Powerdown. To properly terminate Power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from Power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024 clocks are necessary to exit to power down mode and enter in operating mode. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 19. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that puts the T89C51RD2 into Power-down mode.
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Figure 19. Power-down Exit Waveform
INT0 INT1
XTALA or XTALB
Active Phase Power-down Phase Oscillator Restart Phase Active Phase
Exit from Power-down by reset redefines all the SFRs, exit from Power-down by external interrupt does no affect the SFRs. Exit from Power-down by either reset or external interrupt does not affect the internal RAM content.
Note: If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered.
Table 27 shows the state of ports during idle and power-down modes.
Table 27. State of Ports
Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Port Data(1) Floating Port Data(1) Floating PORT1 Port Data Port Data Port Data Port Data PORT2 Port Data Address Port Data Port Data PORT3 Port Data Port Data Port Data Port Data
Port 0 can force a 0 level. A "one" will leave port floating.
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Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 29. (SFR0A7h). Table 28. WDTRST Register WDTRST Address (0A6h)
7 Reset value X 6 X 5 X 4 X 3 X 2 X 1 X
Using the WDT
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. Table 29. WDTPRG Register WDTPRG Address (0A7h)
7 T4 Bit Number 7 6 5 4 3 2 1 6 T3 Bit Mnemonic T4 T3 T2 T1 T0 S2 S1 WDT Time-out select bit 2 WDT Time-out select bit 1 Reserved The value read from this bit is undeterminated. Do not try to set this bit.. Description 5 T2 4 T1 3 T0 2 S2 1 S1 0 S0
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Bit Number 0 Bit Mnemonic S0 Description WDT Time-out select bit 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0Selected Time-out 0(214 - 1) machine cycles, 16.3 ms @ 12 MHz 1(215 - 1) machine cycles, 32.7 ms @ 12 MHz 0(216 - 1) machine cycles, 65.5 ms @ 12 MHz 1(217 - 1) machine cycles, 131 ms @ 12 MHz 0(218 - 1) machine cycles, 262 ms @ 12 MHz 1(219 - 1) machine cycles, 542 ms @ 12 MHz 0(220 - 1) machine cycles, 1.05 s @ 12 MHz 1(221 - 1) machine cycles, 2.09 s @ 12 MHz
Reset value XXXX X000 WDT During Power Down and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the T89C51RD2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T89C51RD2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. If the WDT is activated, the power consumption in stand-by mode will be above the specified value.
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ONCE(TM) Mode (ON Chip The ONCE mode facilitates testing and debugging of systems using T89C51RD2 without removing the circuit from the board. The ONCE mode is invoked by driving certain Emulation)
pins of the T89C51RD2; the following sequence must be exercised: * * Pull ALE low while the device is in reset (RST high) and PSEN is high. Hold ALE low as RST is deactivated.
While the T89C51RD2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 30. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 30. External Pin Status during ONCE Mode
ALE Weak pull-up PSEN Weak pull-up Port 0 Float Port 1 Weak pull-up Port 2 Weak pull-up Port 3 Weak pull-up XTAL1/2 Active
(a) "Once" is a registered trademark of Intel Corporation.
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Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 31. AUXR Register AUXR - Auxiliary Register (8Eh)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. M0 bit: Pulse length in clock period Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0. see table 6 Reserved The value read from this bit is indeterminate. Do not set this bit. XRS1 bit XRAM size: Accessible size of the XRAM. See Table 6. XRS0 bit XRAM size: Accessible size of the XRAM. Table 6. EXTRAM bit See Table 6. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. 5 M0 4 3 XRS1 2 XRS0 1 EXTRAM 0 AO
6
-
5
M0
4
-
3
XRS1
2
XRS0
1
EXTRAM
0
AO
Reset Value = XX0X 1000b Not bit addressable
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EEPROM Data Memory
General Description
The EEPROM memory block contains 2048 bytes and is organized in 32 pages (or rows) of 64 bytes. The necessary high programming voltage is generated on-chip using the standard Vcc pin of the microcontroller. The EEPROM memory block is located at the addresses 0000h to 07FFh of the XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps : write data in the column latches and transfer of all data latches in a EEPROM memory row (programming). The number of data written in the page may vary from 1 to 64 (the page size). When programming, only the data written in the column latch are programmed. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page.
Write Data in the Column Latches
Data is written by byte to the column latches as if it was in an external RAM memory. Out of the 16 address bits of the data pointer, the 10 MSB are used for page selection and 6 are used for byte selection. Between two EEPROM programming, all addresses in the column latches must remain in the same page, thus the 10MSB must be unchanged. The following procedure is used to write in the colums latches : * * * * * Map the program space (Set bit EEE of EECON register) Load DPTR with the address to write Load A register with the data to be written Execute a MOVX @DPTR, A If needed loop the three last instructions until the end of a 64bytes page
Programming
The EEPROM programming consists on the following actions : * write one or more bytes in a page in the column latches. Normally, all bytes must belong to the same page; if this is not the case, the first page address is latched and the others are discarded. Set EETIM with the value corresponding to the XTAL frequency. Launch the programming by writing the control sequence (52h or 50h followed by A2h or A0h) to the EECON register (see Table 32). EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that EEPROM segment is not available for read. The end of programming is signaled by a hardware clear of the EEBUSY flag. ; DPTR = EEPROM data pointer, A = Data to write
MOV ANL JNZ MOV EETIM,#3Ch MOV MOVX MOV MOV .... EECON,#02h @DPTR,A EECON,#50h or 52h EECON,#A0h or A2h A,EECON A,#01h Wait ; 12MHz*5 = 3Ch ; EEE=1 EEPROM mapped ; Write data to EEPROM ; Write Sequence Wait :
* * * *
Example : .....
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Read Data
The following procedure is used to read the data store in the EEPROM memory: * * * Map the program space (Set bit EEE of EECON register) Load DPTR with the address to read Execute a MOVX A, @DPTR ... ; DPTR = EEPROM data pointer
MOV MOVX ... EECON,#02h A,@DPTR ; EEE=1 EEPROM mapped ; Read data from EEPROM ; A = Data
Example :
Registers
Table 32. EECON Register EECON (S:0D2h) EEPROM Control Register
7 EEPL3 6 EEPL2 Bit Mnemonic EEPL3-0 5 EEPL1 4 EEPL0 3 2 1 EEE 0 EEBUSY
Bit Number 7-4 3 2
Description Programming Launch command bits Write 5Xh followed by AXh to EECON to launch the programming. Not implemented, reserved for future use. (1) Not implemented, reserved for future use. (2) Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the data space during MOVX.
1
EEE
0
EEBUSY
Programming Busy flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
2.
Reset Value = XXXX XX00b
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Table 33. EETIM Register EETIM (S:0D3h) EEPROM timing Control Register
7 6 5 4 EETIM Bit Mnemonic 3 2 1 0
Bit Number
Description Write Timer Register
7-0
EETIM
The write timer register value is required to adapt the write time to the oscillator frequency Value = 5 * Fxtal (MHz) in normal mode, 10 * Fxtal in X2 mode. Example : Fxtal = 33 MHZ, EETIM = 0A5h
Reset Value = 0000 0000b
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Flash EEPROM Memory
General Description
The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 64K bytes of program memory organized in 512 pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash. The programming does not require 12v external programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of the microcontroller.
Features
* *
Flash E2PROM internal program memory. The last 1K bytes of the Flash is used to store the low-level in-system programming routines and a default serial loader. If the application does not need to use the ISP and does not expect to modify the Flash content, the Boot Flash sector can be erased to provide access to the full 64K byte Flash memory. Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user. Default loader in Boot Flash allows programming via the serial port without the need of a user provided loader. Up to 64K byte external program memory if the internal program memory is disabled (EA = 0). Programming and erase voltage with standard 5V or 3V VCC supply. Read/Programming/Erase: Byte-wise read (without wait state). Byte or page erase and programming (10 ms). Typical programming time (63K bytes) in 20 s. Parallel programming with 87C51 compatible hardware interface to programmer. Programmable security for the code in the Flash. 100k write cycles 10 years data retention
* * * * * * * * * * * *
Flash Programming and Erasure
The 64K bytes Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to erase a byte or a page before programming. The programming of a byte or a page includes a self erase before programming. There are three methods to program the Flash memory: * * * First, the on-chip ISP bootloader may be invoked which will use low level routines to program the pages. The interface used for serial downloading of Flash is the UART. Second, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot loader. Third, the Flash may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by
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these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the T89C51RD2.
The bootloader and the In Application Programming (IAP) routines are located in the last kilobyte of the Flash, leaving 63k bytes available for the application with ISP.
Flash Registers and Memory Map
The T89C51RD2 Flash memory uses several registers for his management: * * * Flash control register is used to select the Flash memory spaces and launch the Flash programming sequence. Hardware registers can only be accessed through the parallel programming modes which are handled by the parallel programmer. Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space.
Flash Register
Figure 20. FCON register FCON (S:D1h) Flash control register
7 FPL3 Bit Number 7-4 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY
Bit Mnemonic Description FPL3:0 Programming Launch command bits Write 5h followed by Ah to launch the programming. Flash Map Program Space Clear to map the data space during MOVX Set to map the Flash space during MOVX (write) or MOVC (read) instructions (Write in the column latches) Flash Mode Select the addressed space 00: User (0000h-FFFFh) 01: XAF 10: Hardware byte 11: reserved Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be cleared by software
3
FPS
2-1
FMOD1:0
0
FBUSY
Reset Value = xxxx 0000b The Flash programming application note and API source code are available on request. Hardware register The only hardware register of the T89C51RD2 is called Hardware Security Byte (HSB). After full Flash erasure, the content of this byte is FFh; each bit is active at low level.
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7 SB Bit Number
6 BLJB Bit
5 BLLB
4 -
3 -
2 LB2
1 LB1
0 LB0
Mnemonic Description Safe Bit This bit must be cleared to secure the content of the HSB. Only security level can be increased. Boot loader Jump Bit
7
SB
6
BLJB
Set to force hardware boot address at 0000h. (unless previously force by hardware conditions as described in the chapter 9.6). Clear to force hardware boot address at FC03h (default). Boot loader Lock Bit
5
BLLB
Set to allow programming and writing of the boot loader segment. Clear to forbid software programming and writing of the boot loader segment (default). This protection protect only ISP or IAP access; protection through parallel access is done globally by the lock bits LB2-0. Reserved Do not clear this bit. Reserved Do not clear this bit. User Memory Lock Bits See Table 29
4
-
3
-
2-0
LB2-0
Boot Loader Lock Bit (BLLB)
One bit of the HSB is used to secure by hardware the internal boot loader sector against software reprogramming. When the BLLB is cleared, any attempt to write in the boot loader segment (Address FC00h to FFFFh) will have no effect. This protection applies for software writing only. Boot Loader Jump Bit (BLJB) One bit of the HSB, the BLJB bit, is used to force the boot address: * * When this bit is set the boot address is 0000h. When this bit is reset the boot address is FC03h. By default, this bit is cleared and the ISP is enabled.
Flash memory lock bits
The three lock bits provide different levels of protection for the on-chip code and data, when programmed according to Table 29.
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Table 34. Program Lock bits
Program Lock Bits Security level 1 Protection Description LB2 U No program lock features enabled. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled.ISP and software programming with API are still allowed. Same as 2, also verify through parallel programming interface is disabled. Same as 3, also external execution is disabled.
LB0 U
LB1 U
2
P
U
U
3 4
X X
P X
U P
Note: Note: Note: Note:
U: unprogrammed or "one" level. P: programmed or "zero" level. X:do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
These security bits protect the code access through the parallel programming interface. They are set by default to level 4. The code access through the ISP is still possible and is controlled by the "software security bits" which are stored in the extra Flash memory accessed by the ISP firmware. To load a new application with the parallel programmer, a chip erase must first be done. This will set the HSB in its inactive state and will erase the Flash memory, including the boot loader and the "Extra Flash Memory" (XAF). If needed, the 1K boot loader and the XAF content must be programmed in the Flash; the code is provided by ATMEL Wireless and Microcontrollers (see section 8.7. ); the part reference can always be read using Flash parallel programming modes. Default Values The default value of the HSB provides parts ready to be programmed with ISP: * * * * SB: Cleared to secure the content of the HSB. BLJB: Cleared to force ISP operation. BLLB: Clear to protect the default boot loader. LB2-0: Security level four to protect the code from a parallel access with maximum security.
Software Registers
Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by ATMEL Wireless and Microcontrollers ISP (see section 8.7. ). These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: * * Commands issued by the parallel memory programmer. Commands issued by the ISP software.
Calls of API issued by the application software. They are several software registers described in Table 35
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Table 35. Default Values
Mnemonic BSB SBV HSB SSB Boot Status Byte Software Boot Vector Copy of the Hardware security byte Software Security Byte Copy of the Manufacturer Code Copy of the Device ID #1: Family Code Copy of the Device ID #2: memories size and type Copy of the Device ID # 3: name and revision Default Value FFh FCh 18h or 1Bh FFh 58h D7h ATMEL Wireless and Microcontrollers C51 X2, Electrically Erasable
T89C51RD2 memories
FCh size
FFh
T89C51RD2, revision 0
After programming the part by ISP, the BSB must be reset (00h) in order to allow the application to boot at 0000h. The content of the Software Security Byte (SSB) is described in Table 30 and Table 31 To assure code protection from a parallel access, the HSB must also be at the required level. The three lock bits provide different levels of protection for the on-chip code and data, when programmed according to Table 31. Table 36. Program Lock bits of the SSB
Program Lock Bits Security level 1 Protection Description
LB0 U
LB1 U No program lock features enabled. following commands are disabled:
2
P
U
- program byte - program status byte and boot vector - erase status byte and boot vector Same as 2 and following commands also disabled: - read byte
3
X
P
- read status byte and boot vector - blank check - program SSB level2
Note: Note: Note: Note:
U: unprogrammed or "one" level. P: programmed or "zero" level. X:do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
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Flash Memory Status
T89C51RD2 parts are delivered in standard with the ISP boot in the Flash memory. After ISP or parallel programming, the possible contents of the Flash memory are summarized on the figure below:
Figure 21. Flash Memory Possible Contents
FC00h
Boot
Boot
Boot
Boot
Boot
Virgin
Application
Virgin or appli
Application
Virgin or appli
Virgin or appli
Dedicated ISP 0000h Default After ISP After ISP After parallel programming
Dedicated ISP After parallel programming After parallel programming
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Bootloader Architecture
Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 22. Diagram Context Description
Access via Specific Protocol
Bootloader
Flash Memory
Access From User Application
Acronyms
ISP: In-system Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit
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Functional Description Figure 23. Bootloader Functional Description Exernal Host with Specific Protocol Communication
User Application
ISP Communication Management
User Call Management (API )
Flash Memory Management
Flash Memory
On the above diagram, the on-chip bootloader processes are: * ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device. The on-chip ROM implement a serial protocol (see section Bootloader Protocol). This process translate serial communication frame (UART) into Flash memory acess (read, write, erase ...). * User Call Management
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface (API calls), included in the ROM bootloader. The programming functions are selected by setting up the microcontroller's registers before making a call to a common entry point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate the registers values into internal Flash Memory Management.
*
Flash Memory Management
This process manages low level access to Flash memory (performs read and write access).
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Bootloader Functionality Introduction The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user's code but can be manually forced into default ISP operation. As PSEN is an output port in normal operating mode (running user application or boorloader code) after reset, it is recommended to release PSEN after falling edge of reset signal. The hardware conditions are sampled at reset signal falling edge, thus they can be released at any time when reset input is low. The on-chip bootloader boot process is shown in Figure 24.
Purpose Hardware Conditions The Hardware Conditions force the bootloader execution whatever BLJB, BSB and SBV values. The Boot Loader Jump Bit forces the application execution. BLJB = 0 => Boot loader execution. BLJB = 1 => Application execution. BLJB The BLJB is a fuse bit in the Hardware Byte. That can be modified by hardware (programmer) or by software (API). Note: The BLJB test is perform by hardware to prevent any program execution. The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value) if no custumer bootloader in user Flash. SBV Note: The custumer bootloader is called by LJMP [SBV]00h instruction.
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Boot Process Figure 24. Bootloader Process
RESET
Hardware
Hardware Condition?
Yes (PSEN = 0, EA = 1, and ALE = 1 or not connected)
Yes
BLJB = 1 ?
JUMP to FC03h
Software
BSB=0
BSB = 00h ?
SBV = FCh ?
SBV=FCh
SBV=XXh
JUMP to 0000h
JUMP to XX00h
JUMP to FC00h
User Application
User Boot Loader
Default Boot Loader
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ISP Protocol Description
Physical Layer The UART used to transmit information has the following configuration: * * * * * Character: 8-bit data Parity: none Stop: 1 bit Flow control: none Baud rate: autobaud is performed by the bootloader to compute the baud rate choosen by the host.
Frame Description
The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Table 37. Intel Hex Type Frame
Record Mark `:' 1 byte Reclen 1 byte Load Offset 2 bytes Record Type 1 bytes Data or Info n byte Checksum 1 byte
* *
Record Mark: - - Record Mark is the start of frame. This field must contain ':'. Reclen specifies the number of Bytes of information or data which follows the Record Type field of the record. Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this field is used only for Data Program Record (see Section "ISP Commands Summary"). Record Type specifies the command type. This field is used to interpret the remaining information within the frame. The encoding for all the current record types is described in Section "ISP Commands Summary". Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. The two's complement of the 8-bit Bytes that result from converting each pair of ASCII hexadecimal digits to one Byte of binary, and including the Reclen field to and including the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. Reclen:
*
Load Offset: - -
*
Record Type: -
*
Data/Info: -
*
Checksum: -
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Functional Description
Configuration and Manufacturer Information The table below lists Configuration and Manufacturer byte information used by the bootloader. This information can be accessed through a set of API or ISP commands.
Mnemonic BSB SBV SSB Manufacturer Id Id1: Family code Id2: Product Name Id3: Product Revision Description Boot Status Byte Software Boot Vector Software Security Byte Default Value FFh FCh FFh 58h D7h FCh FFh
Software Security Bits (SSB)
The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: * level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. * level 1: WRITE_SECURITY (10h )
For this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns 'P' on write access. From level 1, one can write only level 2. * level 2: RD_WR_SECURITY (00h
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory. The Bootloader returns 'L' on read or write access. Only a full chip erase in parallel mode (using a programmer) or ISP command can reset the software security bits. From level 2, one cannot read and write anything. Table 38. Software Security Byte Behavior
Level 0 Flash/EEPROM Fuse Bit BSB & SBV SSB Any access allowed Any access allowed Any access allowed Any access allowed Level 1 Read only access allowed Read only access allowed Read only access allowed Write level 2 allowed Level 2 Any access not allowed Any access not allowed Any access not allowed Read only access allowed
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Level 0 Manufacturer Info Bootloader Info Erase Block Full-chip Erase Blank Check Read only access allowed Read only access allowed Allowed Allowed Allowed Level 1 Read only access allowed Read only access allowed Not allowed Allowed Allowed Level 2 Read only access allowed Read only access allowed Not allowed Allowed Allowed
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Full Chip Erase
The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some Bytes used by the bootloader at their default values: * * * BSB = FFh SBV = FCh SSB = FFh and finally erase the Software Security Bits
The Full Chip Erase does not affect the bootloader. Checksum Error When a checksum error is detected send `X' followed with CR&LF.
Flow Description
Overview An initialization step must be performed after each Reset. After microcontroller reset, the bootloader waits for an autobaud sequence ( see section `autobaud performance'). When the communication is initialized the protocol depends on the record type requested by the host. FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel the web site. Communication Initialization The host initializes the communication by sending a 'U' character to help the bootloader to compute the baudrate (autobaud). Figure 25. Initialization Host Init Communication "U" Bootloader
Performs Autobaud Sends Back `U' Character
If (not received "U") Else Communication Opened
"U"
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Autobaud Performances The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the T89C51RD2 to establish the baud rate. Table 39 shows the autobaud capability.
Table 39. Autobaud Performances (Bootloader Revision 2.4)
Frequency (MHz) Baudrate (bit/s) 4800 9600 19200 38400 57600 115200 1.8432 OK OK OK 2 OK OK OK OK 2.4576 OK OK OK 3 OK OK OK 3.6864 OK OK OK OK OK 4 OK OK OK OK 5 OK OK OK 6 OK OK OK OK 7.3728 OK OK OK OK OK OK 8 OK OK OK -
Frequency (MHz) Baudrate (bit/s) 4800 9600 19200 38400 57600 115200 10 OK OK OK 11.0592 OK OK OK OK OK OK 12 OK OK OK OK 14.318 OK OK OK OK 14.746 OK OK OK OK OK OK OK OK 16 OK OK 20 OK OK 24 OK OK OK OK 26.6 OK OK OK OK 32 OK OK OK OK
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Command Data Stream Protocol All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader. Figure 26. Command Flow Host Sends first character of the Frame ":" ":" Bootloader If (not received ":") Else Sends echo and start reception
Sends frame (made of 2 ASCII characters per Byte) Echo analysis
Gets frame, and sends back ec for each received Byte
Write/Program Commands
This flow is common to the following frames: * * * * Flash/EEPROM Programming Data Frame EOF or Atmel Frame (only Programming Atmel Frame) Config Byte Programming Data Frame Baud Rate Frame
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Description Figure 27. Write/Program Flow Host
Send Write Command
Bootloader Write Command
Wait Write Command
OR
Wait Checksum Error
Checksum error
'X' & twice (CR & LF)
Send Checksum error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
'P' & CR & LF
Send Security error
COMMAND ABORTED
Wait Programming
Wait COMMAND_OK
'.' & CR & LF
Send COMMAND_OK
COMMAND FINISHED
Example Programming Data (write 55h at address 0010h in the Flash)
HOST BOOTLOADER : 01 0010 00 55 9A : 01 0010 00 55 9A . CR LF
Programming Atmel function (write SSB to level 2)
HOST BOOTLOADER : 02 0000 03 05 01 F5 : 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
HOST BOOTLOADER : 03 0000 03 06 00 55 9F : 03 0000 03 06 00 55 9F . CR LF
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Blank Check Command Description Figure 28. Blank Check Flow Host
Send Blank Check Command
Bootloader Blank Check Command
Wait Blank Check Command
OR
Wait Checksum Error
Checksum error
'X' & twice (CR & LF)
Send Checksum error
COMMAND ABORTED
Flash blank
OR
Wait COMMAND_OK
'.' & CR & LF
Send COMMAND_OK
COMMAND FINISHED
Wait Address not erased
address & CR & LF
Send first Address not erased
COMMAND FINISHED
Example Blank Check ok
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ko at address xxxx
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 70 : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
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Display Data Description Figure 29. Display Flow Host
Send Display Command
Bootloader Display Command
Wait Display Command
OR
Wait Checksum Error
Checksum error
'X' & twice (CR & LF)
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
'L' & CR & LF
Send Security Error
COMMAND ABORTED
Read Data
All data read
Complete Frame
Wait Display Data
"Address = " "Reading value" CR & LF
Send Display Data
All data read
All data read
COMMAND FINISHED
COMMAND FINISHED
Note:
The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.
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Example Display data from address 0000h to 0020h
HOST BOOTLOADER BOOTLOADER BOOTLOADER BOOTLOADER : 05 0000 04 0000 0020 00 D7 : 05 0000 04 0000 0020 00 D7 0000=-----data------ CR LF 0010=-----data------ CR LF 0020=data CR LF (16 data) (16 data) ( 1 data)
Read Function This flow is similar for the following frames: * * Description Figure 30. Read Flow Host
Send Read Command
Reading Frame EOF Frame/Atmel Frame (only reading Atmel Frame)
Bootloader Read Command
Wait Read Command
OR
Wait Checksum Error
Checksum error
'X' & twice (CR & LF)
Send Checksum error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
'L' & CR & LF
Send Security error
COMMAND ABORTED
Read Value
Wait Value of Data
'value' & '.' & CR & LF
Send Data Read
COMMAND FINISHED
Example Read function (read SBV)
HOST BOOTLOADER : 02 0000 05 07 02 F0 : 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read Bootloader version)
HOST BOOTLOADER : 02 0000 01 02 00 FB : 02 0000 01 02 00 FB Value . CR LF
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ISP Commands Summary Table 40. ISP Commands Summary
Command Command Name Data[0] Data[1] Command Effect Program Nb Data Byte. 00h Program Data Bootloader will accept up to 16 (10h) data Bytes. The data Bytes should be 128 Byte page Flash boundary. 04h 05h 01h 03h Write Function 06h 01h 07h Program SBV (value to write in data[2]) Full Chip Erase Display Data 00h Program SSB level 2 Program BSB (value to write in data[2]) 00h 00h Erase SBV Program SSB level 1
Data[0:1] = start address 04h Display Function Data [2:3] = end address
Data[4] = 00h -> Display data Blank Check Data[4] = 01h -> Blank check 00h 01h 00h 02h 03h 00h Device ID #2 Device ID #3 Read SSB Read BSB Read SBV Read Hardware Byte Copy Read Bootloader Version Read Device Boot ID1 Read Device Boot ID2 Manufacturer ID Device ID #1
05h
Read Function 07h
01h 02h 03h 08h 0Eh 01h 00h 00h
API Call Description
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FFF0h. Results are returned in the registers. When several Bytes have to be programmed, it is highly recommended to use the Atmel API "PROGRAM DATA PAGE" call. Indeed, this API call writes up to 128 Bytes in a single command. All routines for software access are provided in the C Flash driver available at Atmel's web site.
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The API calls description and arguments are shown in Table 41. Table 41. API Call Summary
Command READ MANUF ID READ DEVICE ID1 READ DEVICE ID2 READ DEVICE ID3 PROGRAM DATA BYTE ERASE BOOT VECTOR R1 00h 00h 00h 00h 02h A XXh XXh XXh XXh Byte value to program XXh DPTR0 0000h 0001h 0002h 0003h Address of Byte to program XXh DPH = 00h DPL = 00h DPH = 00h DPL = 01h PROGRAM SSB 05h XXh DPH = 00h DPL = 10h DPH = 00h DPL = 11h PROGRAM BSB PROGRAM SBV READ SSB READ HSB READ BSB READ SBV PROGRAM DATA PAGE 06h 06h 07h 07h 07h 07h New BSB value New SBV value XXh XXh XXh XXh Number of Byte to program XXh XXh XXh 0000h 0001h 0000h 0004h 0001h 0002h Address of the first Byte to program in the Flash memory DPL = 00h DPL = 01h XXXXh XXh XXh XXh XXh XXh XXh Address in XRAM of the first data to program XXh XXh XXh none none ACC=SSB ACC=HSB ACC=BSB ACC=SBV 00h ACC= SSB value Set SSB level 0 XXh DPTR1 XXh XXh XXh XXh Returned Value ACC=Manufacturer ID ACC= Device ID 1 ACC=Device ID 2 ACC=Device ID 3 ACC = 0 : DONE Command Effect Read Manufacturer identifier Read Device identifier 1 Read Device identifier 2 Read Device identifier 3 Program one Data Byte in user Flash Erase Software boot vector and boot status Byte. (SBV=FCh and BSB=FFh) Set SSB level 1
04h
ACC=FCh
Set SSB level 2
Set SSB level 1 Program boot status Byte Program software boot vector Read Software Security Byte Read Hardware Byte Read Boot Status Byte Read Software Boot Vector Program up to 128 Bytes in user Flash. ACC = 0 : DONE Remark: number of Bytes to program is limited such as the Flash write remains in a single 128 Bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or 80h. Read boot ID1 Read boot ID2 Read bootloader version
09h
READ BOOT ID1 READ BOOT ID2 READ BOOT VERSION
0Eh 0Eh 0Fh
ACC=ID1 ACC=ID2 ACC=Boot_Version
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Flash Parallel Programming
Signature Bytes Four hardware read only registers have to be accessed with parallel static test modes (mode TMS) in order to control the Flash parallel programmimg: * * * * Manufacturer code Device ID # 1: Family code Device ID # 2: Memories size and type Device ID # 3: Name and revision
As these registers can only be accessed by hardware, they must be read by the parallel programmers and then copied in the XAF in order to make their values accessible by software (ISP or API). Set-up modes Configuration In order to program and verify the Flash or to read the signature bytes, the T89C51RD2 is placed in specific set-up modes. (See Figure 31.)
Figure 31. Set-Up Modes Configuration
+5V PROGRAM SIGNALS* EA ALE/PROG P0.0-P0.7 RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 XTAL1 D0-D7 VCC
P1.0-P1.7 P2.0-P2.5 P3.4 P3.5
A0-A7 A8-A13 A14 A15
CONTROL SIGNALS*
4 to 6 MHz
VSS GND
Definition of Terms
Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4-P3.5, respectively for A0-A15. Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.2, P3.3, P3.6, P3.7. Program Signals: ALE/PROG, EA
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Set-up modes configuration
Control and program signals must be held at the levels indicated in the two following tables.
Mode Name PELCK
Mode Program or Erase Lock. Disable the Erasure or Programming access Program or Erase UnLock. Enable the Erasure or Programming access Write Code Data (byte)
Rst 1
Psen 0
Ale __ |_| __ |_| Note 2 __
EA 1
P2.6 1
P2.7 0
P3.6 1
P3.7 0
P0[7..0] xx
PEULCK
1
0
1
1
0
1
0
55-AA
PGMC
or write Page Always precedeed by PGML Memory Page Load (up to 128 bytes) Read Code Data (byte)
1
0
|_| Internally timed Note 1
1
0
1
1
1
xx
PGML
1
0
1
0
1 __ |_| __ |_| 1 0
0
1
Din
PGMV
1
0
1
1
0
1
1
Dout
VSB
Read Security Byte (=HSB) Write Security Byte (Note 3) (security byte = HSB) Chip Erase User + XAF
1
0
1
1
0
0
1
Dout
PGMS CERR
1 1
0 0
10 ms 100 ms __
1 1
1 1
0 0
0 0
Din xx
PGXC
Write Byte or Page in Extra Memory (XAF) Always precedeed by PGXL
1
0
|_| Internally timed Note 1
1
1
1
0
1
xx
PGXL
Memory Page Load XAF (up to 128 bytes) Read Signature bytes 30h (Manufacturer code)
1
0
1
1
1
0
1
Din Dout =
__ 1 0 1 1 0 |_| 0 0
58h D7h FCh FFh
TMS
31h (Device ID #1) 60h (Device ID #2) 61h (Device ID #3)
RXAF
Read Extra Memory (XAF)
1
0
1
1
0
__ |_|
0
0
Dout
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Mode Name PELCK
Mode Program or Erase Lock. Disable the Erasure or Programming access Program or Erase UnLock. Enable the Erasure or Programming access Write Code Data (byte)
P1[7..0] xx
P2[5..0] xx
P3.0 x
P3.1 x
P3.2 x
P3.3 1
P3.4 x
P3.5 x
PEULCK
xx
xx
x
x
x
0
x
x
PGMC
or write Page Always precedeed by PGML
A7-A0
A13-A8
1
x
x
0
A14
A15
PGML PGMV VSB PGMS CERR PGXC
Memory Page Load (up to 128 bytes) Read Code Data (byte) Read Security Byte (=HSB) Write lock Byte (Note 4) (security byte = HSB) Chip Erase User + XAF Write Byte or Page Extra Memory (XAF) Always precedeed by PGXL Memory Page Load XAF (up to 128 bytes) Read Signature bytes 30h (Manufacturer code)
A7-A0 A7-A0 xx xx xx A7-A0 (0-7F) A7-A0 (0-7F) 30h 31h 60h 61h Addr (0-7F)
A13-A8 A13-A8 xx xx xx xx
1 1 1 1 1 1
x x x x x x
x x x x x x
0 1 1 0 0 0
A14 A14 x x x x
A15 A15 x x x x
PGXL
xx
1
x
x
1
x
x
TMS
31h (Device ID #1) 60h (Device ID #2) 61h (Device ID #3)
x
x
x
x
1
x
x
RXAF
Read Extra Memory (XAF)
00
1
x
x
0
x
x
1. In Page Load Mode the current byte is loaded on ALE rising edge. 2. After a power up all external test mode to program or to erase the Flash are locked to avoid any untimely programming or erasure. After each programming or erasure test mode, it's advised to lock this feature (test mode PELCK). To validate the test mode mode PEULCK the following sequence has to be applied:Test Mode PEULCK with ALE = 1. Pulse on ALE (min width=25clk) with P0=55 (P0 latched on ALE rising edge) Pulse on ALE (min width=25clk) with P0=AA (P0 latched on ALE rising edge) 3. The highest security bit (bit 7) is used to secure the 7 lowest bit erasure. The only way to erase this bit is to erase the whole Flash memory. Procedure to program security bits (After array programming): - program bit7 to 0, program all other bits ( 1 = erased, 0 = programmed). - test mode PGMS (din = HSB). Procedure to erase security byte: - test mode CERR: erase all array included HSB. - program hardware security byte to FF: test mode PGMS (din = FF).
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Programming Algorithm
To program the T89C51RD2 the following sequence must be exercised: * * Check the signature bytes Check the HSB (VSB mode)
If the security bits are activated, the following commands must be done before programming: * * * * * * Unlock test modes (PEULCK mode, pulse 55h and AAh) Chip erase (CERR mode) Write FFh in the HSB (PGMS mode) Write the signature bytes content in the XAF As the boot loader and the XAF content is lost after a "chip erase", it must be reprogrammed if needed. Disable programming access (PELCK mode)
To write a page in the Flash memory, execute the following steps: * * * * * * * * * * Step 0: Enable programming access (PEULCK mode) Step 1: Activate the combination of control signals (PGML mode) Step 2: Input the valid address on the address lines (High order bits of the address must be stable during the complete ALE low time) Step 3: Activate the combination of control signals (PGML mode) Step 4: Input the appropriate data on the data lines. Step 5: Pulse ALE/PROG once. Step 6: Enable programming access (PEULCK mode) Step 7: Activate the combination of control signals (PGMC mode) Step 8: Input the valid address on the address lines. Step 9: Pulse ALE/PROG once the specified write time is reached.
Repeat step 2 through 5 changing the address and data for end of a 128 bytes page
Repeat step 0 through 9 changing the address and data until the entire array or until the end of the object file is reached (See Figure 32.) * Step 10: Disable programming access (PELCK mode)
Verify Algorithm
Verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the T89C51RD2. P 2.7 is used to enable data output. To verify the T89C51RD2 code the following sequence must be exercised: * * * Step 1:Activate the combination of program and control signals (PGMV) Step 2: Input the valid address on the address lines. Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 32.).
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Figure 32. Programming and Verification Signal's Waveform
Programming Cycle A0-A15 D0-D7 Data In Data Out 48 clk (load latch ) or 10 ms (write) or 100 ms (erase) ALE/PROG Read/Verify Cycle
EA Control signals
5V 0V
P2.7
Extra Memory Mapping
The memory mapping the T89C51RD2 software registers in the Extra Flash memory is described in the table below. Table 42. Extra Row Memory Mapping (XAF)
Address Copy of device ID #3 Copy of device ID #2 Copy of device ID #1 Copy of Manufacturer Code: 0061h 0060h 0031h 0030h Default content FFh FCh D7h 58h
ATMEL
Software Security Byte (level 1 by default) Copy of HSB (level 4 by default and BLJB = 0) Software Boot Vector Boot Status Byte
0005h
FFh
0004h 0001h 0000h
18h or 1Bh FCh FFh
All other addresses are reserved
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Electrical Characteristics
Absolute Maximum Ratings
*NOTICE:
Ambiant Temperature Under Bias: C = commercial .......................................... 0C to 70C I = industrial ............................................. -40C to 85C Storage Temperature ..........................-65C to +150C Voltage on VCC VSS ................................ -0.5 V to +6.5V Voltage on Any Pin VSS ................... -0.5 V to VCC+0.5 V Power Dissipation .................................................1 W(2)
Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package.
DC Parameters for Standard Voltage
TA = 0C to +70C; VSS = 0 V; VCC = 5 V 10%; F = 0 to 40 MHz. TA = -40C to +85C; VSS = 0 V; VCC = 5 V 10%; F = 0 to 40 MHz. Table 43. DC Parameters in Standard Voltage (1)
Symbol VIL VIH VIH1 Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Min -0.5 0.2 VCC + 0.9 0.7 VCC
(6)
Typ (5)
Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.3
Unit V V V V V V V V V V V V
Test Conditions
IOL = 100 A(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOL = 200 A(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) IOH = -10 A IOH = -30 A IOH = -60 A VCC = 5 V 10% IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V 10%
VOL
Output Low Voltage, ports 1, 2, 3, 4 and 5
0.45 1.0 0.3
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
0.45 1.0 VCC - 0.3
VOH
Output High Voltage, ports 1, 2, 3, 4 and 5
VCC - 0.7 VCC - 1.5
VCC - 0.3 VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.7 VCC - 1.5 RRST IIL ILI ITL RST Pulldown Resistor Logical 0 Input Current ports 1, 2, 3, 4 and 5 Input Leakage Current for P0 only Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 and 5 50 90 200 -50 10 -650
V V V k A A A
Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V
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Table 43. DC Parameters in Standard Voltage (1)
Symbol CIO IPD Parameter Capacitance of I/O Buffer Power Down Current Power Supply Current on normal mode ICCOP 120 Min Typ (5) Max 10 150 0.7 Freq (MHz) + 3 Unit pF A Test Conditions Fc = 1 MHz TA = 25C VCC = 3 V to 5.5 V(3) VCC = 5.5 V(1)
mA
Power Supply Current during Flash Write / Erase ICCProgFlash
0.3 Freq (MHz) + 10
0.4 Freq (MHz) + 12
mA
VCC = 5.5 V(1)
ICCProgEE
Power Supply Current during EEprom data Write / Erase
0.7 Freq (MHz) + 3
0.7 Freq (MHz) + 18
mA
VCC = 5.5 V(1)
ICCIDLE
Power Supply Current on idle mode
0.4 Freq (MHz) + 2
mA
VCC = 5.5 V(2)
DC Parameters for Standard Voltage (2)
TA = 0C to +70C; VSS = 0 V; VCC = 3 V to 5.5 V; F = 0 to 33 MHz. TA = -40C to +85C; VSS = 0 V; VCC = 3 V to 5.5 V; F = 0 to 33 MHz. Table 44. DC Parameters for Standard Voltage (2)
Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ILI ITL RRST CIO IPD ICCOP Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3, 4 and 5 Output Low Voltage, port 0, ALE, PSEN (6) Output High Voltage, ports 1, 2, 3, 4 and 5 Output High Voltage, port 0, ALE, PSEN Logical 0 Input Current ports 1, 2, 3, 4 and 5 Input Leakage Current for P0 only Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 and 5 RST Pulldown Resistor Capacitance of I/O Buffer Power Down Current Power Supply Current on normal mode 120 50 90 0.9 VCC 0.9 VCC -50 10 -650 200 10 150 0.7 Freq (MHz) + 3 mA
(6)
Min -0.5 0.2 VCC + 0.9 0.7 VCC
Typ(5)
Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45
Unit V V V V V V V A A A k pF A
Test Conditions
IOL = 0.8 mA(4) IOL = 1.6 mA(4) IOH = -10 A IOH = -40 A Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V
Fc = 1 MHz TA = 25C VCC = 3 V to 5.5 V(3) VCC = 5.5 V(1)
mA
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Table 44. DC Parameters for Standard Voltage (2)
Symbol Parameter Power Supply Current during Flash Write / Erase ICCProgFlash Min Typ(5) Max Unit Test Conditions
0.3 Freq (MHz) + 10
0.4 Freq (MHz) + 12
mA
VCC = 5.5 V(1)
ICCProgEE
Power Supply Current during EEprom data Write / Erase
0.7 Freq (MHz) + 3
0.7 Freq (MHz) + 18
mA
VCC = 5.5 V(1)
ICCIDLE
Power Supply Current on idle mode
0.5 Freq (MHz) + 2 mA
mA
VCC = 5.5 V(2)
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DC Parameters for Low Voltage
TA = 0C to +70C; VSS = 0 V; VCC = 2.7 V to 3.6 V; F = 0 to 25 MHz TA = -40C to +85C; VSS = 0 V; VCC = 2.7 V to 3.6 V; F = 0 to 25 MHz Table 45. DC Parameters for Low Voltage
Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ILI ITL RRST CIO IPD ICCOP Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3, 4 and 5 (6) Output Low Voltage, port 0, ALE, PSEN (6) Output High Voltage, ports 1, 2, 3, 4 and 5 Output High Voltage, port 0, ALE, PSEN Logical 0 Input Current ports 1, 2, 3, 4 and 5 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 and 5 RST Pulldown Resistor Capacitance of I/O Buffer Power Down Current Power Supply Current on normal mode 1 50 90 0.9 VCC 0.9 VCC -50 10 -650 200 10 50 0.6 Freq (MHz) +3 Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ(5) Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V A A A k pF A Fc = 1 MHz TA = 25C VCC = 2.7 V to 3.6 V(3) VCC = 3.6 V(1) VCC = 3.6 V(1) IOL = 0.8 mA(4) IOL = 1.6 mA(4) IOH = -10 A IOH = -40 A Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V Test Conditions
mA
Power Supply Current during Flash Write / Erase ICCProgFlash
0.3 Freq (MHz) + 10
0.4 Freq (MHz) + 12
mA
ICCProgEE
Power Supply Current during EEprom data Write / Erase
0.7 Freq (MHz) + 3
0.7 Freq (MHz) + 18
mA
VCC = 3.6 V(1)
ICCIDLE
Power Supply Current on idle mode
0.3 Freq (MHz) +2
mA
VCC = 3.6 V(2)
4. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 36.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 33.). 5. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 34.). 6. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 35.). In addition, the WDT must be inactive and the POF flag must be set. 7. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
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transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 8. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.. 9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
Figure 33. ICC Test Condition, Active Mode
VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC
Figure 34. ICC Test Condition, Idle Mode
VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
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Figure 35. ICC Test Condition, Power-Down Mode
VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1
Figure 36. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = 0 to +70C; VSS = 0 V; VCC = 5 V 10%; M range. TA = -40C to +85C; VSS = 0 V; VCC = 5 V 10%; M range. TA = 0 to +70C; VSS = 0 V; 2.7 V < VCC < 3.3 V; L range. TA = -40C to +85C; VSS = 0 V; 2.7 V < VCC < 3.3 V; L range. AC characteristics of -M parts at 3 volts are similar to -L parts (Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.) Table 44, Table 48 and Table 50 give the description of each AC symbols. Table 46, Table 49 and Table 51 give for each range the AC parameter. Table 47, Table 50 and Table 52 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value in the correponding column (-M or -L) and use this value in the formula. Example: TLLIU for -M and 20 MHz, Standard clock. x = 35 ns T = 50 ns TCCIV = 4T - x = 165 ns 85
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External Program Memory Characteristics
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Parameter Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float
Table 46. AC Parameters for a Fix Clock
Symbol Min T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 18 85 10 15 55 35 0 18 85 10 25 40 10 10 70 15 55 35 -M Max Min 25 40 10 10 70 -L Max ns ns ns ns ns ns ns ns ns ns ns ns Units
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Table 47. AC Parameters for a Variable Clock
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x X parameter for - X parameter for M range L range 10 15 15 30 10 20 40 0 7 40 10 10 15 15 30 10 20 40 0 7 40 10 Units ns ns ns ns ns ns ns ns ns ns ns
External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ
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External Data Memory Characteristics Table 48. Symbol Description
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high
Table 49. AC Parameters for a Fix Clock
Symbol Min TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH 10 50 75 10 160 15 0 40 10 0 30 160 165 100 50 75 10 160 15 0 40 130 130 100 0 30 160 165 100 -M Max Min 130 130 100 -L Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
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Table 50. AC Parameters for a Variable Clock
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x X parameter for - X parameter for M range L range 20 20 25 0 20 40 60 25 25 25 15 15 10 0 15 15 20 20 25 0 20 40 60 25 25 25 15 15 10 0 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
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External Data Memory Read Cycle
ALE TLLDV TWHLH
PSEN
TLLWL
TRLRH
RD TAVDV TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDX DATA IN
TRHDZ
Serial Port Timing - Shift Register Mode
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Table 51. AC Parameters for a Fix Clock
Symbol Min TXLXL TQVHX TXHQX TXHDX TXHDV 300 200 30 0 117 -M Max Min 300 200 30 0 117 -L Max ns ns ns ns ns Units
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Table 52. AC Parameters for a Variable Clock
X parameter for - X parameter for M range L range
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV
Type Min Min Min Min Max
Standard Clock 12 T 10 T - x 2T-x x 10 T - x
X2 Clock 6T 5T-x T-x x 5 T- x
Units ns
50 20 0 133
50 20 0 133
ns ns ns ns
Shift Register Timing Waveforms
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV VALID VALID TXHQX 1 2 TXHDX VALID VALID VALID VALID VALID 3 4 5 6 7 SET TI VALID SET RI 0 1 2 3 4 5 6 7 8
Flash EEPROM Programming and Verification Characteristics
TA = 21C to 27C; VSS = 0V; VCC = 5V 10%.
Table 53. Flash Programming Parameters
Symbol 1/TCLCL TEHAZ TAVGL TGHAX TDVGL TGHDX TGLGH TGLGH TAVQV TELQV TEHQZ Parameter Oscillator Frquency Control to address float Address Setup to PROG Low Adress Hold after PROG Data Setup to PROG Low 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 10 48 TCLCL 48 TCLCL 48 TCLCL 0 48 TCLCL 20 ms Min 4 Max 6 48 TCLCL Units MHz
Data Hold after PROG
PROG Width for PGMC and PGXC* PROG Width for PGML Address to Valid Data ENABLE Low to Data Valid Data Float after ENABLE
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Flash EEPROM Programming and Verification Waveforms
PROGRAMMING P1.0-P1.7 P2.0-P2.4 P3.4-P3.5 P0 TDVGL TAVGL ALE/PROG TGLGH CONTROL SIGNALS (ENABLE) TEHAZ TELQV TEHQZ ADDRESS VERIFICATION ADDRESS TAVQV DATA IN TGHDX TGHAX DATA OUT
External Clock Drive Characteristics (XTAL1) Table 54. AC Parameters
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 25 5 5 5 5 60 Max Units ns ns ns ns ns %
External Clock Drive Waveforms
VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH
AC Testing Input/Output Waveforms
VCC -0.5 V INPUT/OUTPUT 0.45 V 0.2 VCC + 0.9 0.2 VCC - 0.1
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AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min for a logic "1" and VIL max for a logic "0". Float Waveforms
FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20mA.
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Clock Waveforms
STATE4 P1 P2
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2
INTERNAL
CLOCK XTAL2 ALE
EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE RD PCL OUT DATA SAMPLED FLOAT INDICATES ADDRESS TRANSITIONS
THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION
PCL OUT
DATA SAMPLED FLOAT
PCL OUT
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
DATA SAMPLED FLOAT
P2 WRITE CYCLE
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WR P0
DPL OR Rt OUT DATA OUT P2
PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED OLD DATA NEW DATA P0 PINS SAMPLED P0 PINS SAMPLED
RXD SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
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Ordering Information
Part Number Memory Size 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Supply Voltage 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 4.5 - 5.5V 4.5 - 5.5V 4.5 - 5.5V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 4.5 - 5.5V 4.5 - 5.5V 2.7 - 3.6V Temperature Range Commercial Commercial Industrial Industrial Commercial Commercial Commercial Industrial Industrial Industrial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Commercial Commercial Industrial Industrial Commercial Industrial Industrial Package PDIL40 PDIL40 PDIL40 PDIL40 Dice VQFP64 VQFP64 VQFP64 VQFP64 VQFP64 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 VQFP44 PLC44 PLC44 PLC44 PLC44 PLC44 PLC44 PLC44 PLC44 PLC44 PLCC68 Packing Stick Stick Stick Stick Tray & Dry Pack Tray Tray Tray Tray Tray + Dry Pack Tape & Reel + Dry Pack Tape & Reel + Dry Pack Tape & Reel Tray Tray Tray Tray Tray + Dry Pack Tray + Dry Pack Tray + Dry Pack Tray + Dry Pack Tape & Reel + Dry Pack Tape & Reel Tape & Reel Stick Stick Stick Stick Stick + Dry Pack Stick + Dry Pack Tape & Reel
T89C51RD2-3CSCL T89C51RD2-3CSCM T89C51RD2-3CSIL T89C51RD2-3CSIM T89C51RD2-DDVCM T89C51RD2-RDTCL T89C51RD2-RDTCM T89C51RD2-RDTIL T89C51RD2-RDTIM T89C51RD2-RDVIM T89C51RD2-RLFCM T89C51RD2-RLFIM T89C51RD2-RLRIM T89C51RD2-RLTCL T89C51RD2-RLTCM T89C51RD2-RLTIL T89C51RD2-RLTIM T89C51RD2-RLVCL T89C51RD2-RLVCM T89C51RD2-RLVIL T89C51RD2-RLVIM T89C51RD2-SLFCL T89C51RD2-SLRCM T89C51RD2-SLRIM T89C51RD2-SLSCL T89C51RD2-SLSCM T89C51RD2-SLSIL T89C51RD2-SLSIM T89C51RD2-SLUCM T89C51RD2-SLUIM T89C51RD2-SMRIL
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Part Number
Memory Size 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Supply Voltage 2.7 - 3.6V 4.5 - 5.5V 2.7 - 3.6V 4.5 - 5.5V 4.5 - 5.5V 4.5 - 5.5V
Temperature Range Commercial Commercial Industrial Industrial Commercial Industrial
Package PLCC68 PLCC68 PLCC68 PLCC68 PLCC68 PLCC68
Packing Stick Stick Stick Stick Stick + Dry Pack Stick + Dry Pack
T89C51RD2-SMSCL T89C51RD2-SMSCM T89C51RD2-SMSIL T89C51RD2-SMSIM T89C51RD2-SMUCM T89C51RD2-SMUIM
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Package Drawings
DIL40
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PLCC44
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VQFP44
99
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VQFP64
100
T89C51RD2
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T89C51RD2
PLCC68
101
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VQFP64
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Datasheet Change Log for T89C51RD2
Changes from 4243F02/01 to 4243G-05/03
1. Added bootloader ISP protocol description.
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